golden hour

/usr/include/linux

File/Folder	Size	Actions
a.out.h	7.15 KB
acct.h	3.58 KB
adb.h	1.05 KB
adfs_fs.h	873 B
affs_hardblocks.h	1.45 KB
agpgart.h	3.83 KB
aio_abi.h	3.18 KB
apm_bios.h	3.46 KB
arcfb.h	150 B
atalk.h	960 B
atm.h	7.64 KB
atm_eni.h	585 B
atm_he.h	343 B
atm_idt77105.h	892 B
atm_nicstar.h	1.19 KB
atm_tcp.h	1.52 KB
atm_zatm.h	1.57 KB
atmapi.h	889 B
atmarp.h	1.2 KB
atmbr2684.h	3.13 KB
atmclip.h	513 B
atmdev.h	7.44 KB
atmioc.h	1.55 KB
atmlec.h	2.26 KB
atmmpc.h	4.07 KB
atmppp.h	576 B
atmsap.h	4.79 KB
atmsvc.h	1.75 KB
audit.h	17.83 KB
auto_fs.h	2.53 KB
auto_fs4.h	4.23 KB
auxvec.h	1.4 KB
ax25.h	2.7 KB
b1lli.h	1.62 KB
baycom.h	820 B
beancounter.h	2.38 KB
bfs_fs.h	1.79 KB
binfmts.h	565 B
blkpg.h	1.56 KB
blktrace_api.h	4.38 KB
bpqether.h	952 B
bsg.h	2.37 KB
bt-bmc.h	508 B
btrfs.h	25.07 KB
byteorder	-
caif	-
can	-
can.h	5.46 KB
capability.h	10.92 KB
capi.h	2.99 KB
cciss_defs.h	3.14 KB
cciss_ioctl.h	2.63 KB
cdrom.h	28.12 KB
cgroupstats.h	2.1 KB
chio.h	5.16 KB
cm4000_cs.h	1.68 KB
cn_proc.h	3.19 KB
coda.h	17.09 KB
coda_psdev.h	720 B
coff.h	12.12 KB
compat.h	9.63 KB
connector.h	2.14 KB
const.h	673 B
cramfs_fs.h	2.68 KB
cuda.h	842 B
cyclades.h	16.65 KB
cycx_cfm.h	2.86 KB
dcbnl.h	24.19 KB
dccp.h	6.22 KB
devlink.h	7.09 KB
dlm.h	2.43 KB
dlm_device.h	2.42 KB
dlm_netlink.h	1.04 KB
dlm_plock.h	831 B
dlmconstants.h	4.9 KB
dm-ioctl.h	10.55 KB
dm-log-userspace.h	14.82 KB
dn.h	4.42 KB
dqblk_xfs.h	8.72 KB
dvb	-
edd.h	5.41 KB
efs_fs_sb.h	2.11 KB
elf-em.h	1.83 KB
elf-fdpic.h	1.04 KB
elf.h	12.63 KB
elfcore.h	2.86 KB
errno.h	23 B
errqueue.h	1.1 KB
ethtool.h	68.76 KB
eventpoll.h	1.76 KB
fadvise.h	855 B
falloc.h	1.98 KB
fanotify.h	3.52 KB
fb.h	16 KB
fcntl.h	2.16 KB
fd.h	11.31 KB
fdreg.h	5.23 KB
fib_rules.h	1.57 KB
fiemap.h	2.65 KB
filter.h	3.53 KB
firewire-cdev.h	42.86 KB
firewire-constants.h	3.16 KB
flat.h	2.04 KB
fou.h	617 B
fs.h	9.84 KB
fsl_hypervisor.h	7.05 KB
fuse.h	16.22 KB
futex.h	4.81 KB
gameport.h	834 B
gen_stats.h	1.48 KB
genetlink.h	1.85 KB
gfs2_ondisk.h	12 KB
gigaset_dev.h	1.35 KB
hdlc	-
hdlc.h	574 B
hdlcdrv.h	2.78 KB
hdreg.h	22.11 KB
hid.h	1.79 KB
hiddev.h	6.13 KB
hidraw.h	1.41 KB
hpet.h	680 B
hsi	-
hw_breakpoint.h	679 B
hyperv.h	10.22 KB
hysdn_if.h	1.29 KB
i2c-dev.h	2.37 KB
i2c.h	6.61 KB
i2o-dev.h	11.22 KB
i8k.h	1.4 KB
icmp.h	2.82 KB
icmpv6.h	3.82 KB
if.h	9.36 KB
if_addr.h	1.7 KB
if_addrlabel.h	658 B
if_alg.h	816 B
if_arcnet.h	3.63 KB
if_arp.h	6.3 KB
if_bonding.h	4.11 KB
if_bridge.h	6.46 KB
if_cablemodem.h	922 B
if_eql.h	1.26 KB
if_ether.h	7.13 KB
if_fc.h	1.63 KB
if_fddi.h	3.6 KB
if_frad.h	2.89 KB
if_hippi.h	4.07 KB
if_infiniband.h	1.13 KB
if_link.h	19.1 KB
if_ltalk.h	147 B
if_macsec.h	5.42 KB
if_packet.h	7.15 KB
if_phonet.h	361 B
if_plip.h	596 B
if_ppp.h	29 B
if_pppol2tp.h	3.18 KB
if_pppox.h	4.64 KB
if_slip.h	809 B
if_team.h	2.48 KB
if_tun.h	3.77 KB
if_tunnel.h	3 KB
if_vlan.h	1.69 KB
if_x25.h	817 B
ife.h	288 B
igmp.h	2.88 KB
in.h	9.15 KB
in6.h	6.99 KB
in_route.h	873 B
inet_diag.h	3.23 KB
inotify.h	3.09 KB
input.h	32.47 KB
ioctl.h	100 B
ip.h	3.47 KB
ip6_tunnel.h	1.67 KB
ip_vs.h	12.71 KB
ipc.h	1.99 KB
ipmi.h	15.8 KB
ipmi_msgdefs.h	4.37 KB
ipsec.h	884 B
ipv6.h	3.25 KB
ipv6_route.h	1.69 KB
ipx.h	1.79 KB
irda.h	7.31 KB
irqnr.h	104 B
isdn	-
isdn.h	5.58 KB
isdn_divertif.h	1.11 KB
isdn_ppp.h	1.82 KB
isdnif.h	2.25 KB
iso_fs.h	6.29 KB
ivtv.h	2.89 KB
ivtvfb.h	1.12 KB
ixjuser.h	24.53 KB
jffs2.h	6.85 KB
joystick.h	3.5 KB
kd.h	6.04 KB
kdev_t.h	320 B
kernel-page-flags.h	767 B
kernel.h	375 B
kernelcapi.h	956 B
kexec.h	1.92 KB
keyboard.h	12.42 KB
keyctl.h	2.98 KB
kvm.h	33.97 KB
kvm_para.h	819 B
l2tp.h	4.98 KB
libc-compat.h	3.44 KB
limits.h	874 B
llc.h	2.98 KB
loop.h	2.31 KB
lp.h	3.72 KB
lwtunnel.h	839 B
magic.h	2.91 KB
major.h	4.48 KB
map_to_7segment.h	7.02 KB
matroxfb.h	1.37 KB
mdio.h	13.74 KB
media.h	3.5 KB
mei.h	4.62 KB
memfd.h	186 B
mempolicy.h	2.35 KB
meye.h	2.41 KB
mii.h	7.76 KB
minix_fs.h	2.01 KB
mman.h	230 B
mmc	-
mmtimer.h	2.01 KB
mpls.h	1.33 KB
mqueue.h	2.01 KB
mroute.h	4.12 KB
mroute6.h	4.08 KB
msdos_fs.h	6.28 KB
msg.h	2.55 KB
mtio.h	7.92 KB
n_r3964.h	2.29 KB
nbd.h	2.34 KB
ncp.h	4.94 KB
ncp_fs.h	3.27 KB
ncp_mount.h	2.06 KB
ncp_no.h	651 B
ndctl.h	8.79 KB
neighbour.h	4.17 KB
net.h	1.97 KB
net_dropmon.h	1.07 KB
net_namespace.h	609 B
net_tstamp.h	4.06 KB
netconf.h	423 B
netdevice.h	1.46 KB
netfilter	-
netfilter.h	1.56 KB
netfilter_arp	-
netfilter_arp.h	380 B
netfilter_bridge	-
netfilter_bridge.h	768 B
netfilter_decnet.h	1.83 KB
netfilter_ipv4	-
netfilter_ipv4.h	2.02 KB
netfilter_ipv6	-
netfilter_ipv6.h	2.04 KB
netlink.h	6.22 KB
netlink_diag.h	1.33 KB
netrom.h	744 B
nfc.h	7.72 KB
nfs.h	4.31 KB
nfs2.h	1.37 KB
nfs3.h	2.24 KB
nfs4.h	5.95 KB
nfs4_mount.h	1.83 KB
nfs_fs.h	1.51 KB
nfs_idmap.h	2.19 KB
nfs_mount.h	2.32 KB
nfsacl.h	605 B
nfsd	-
nl80211.h	226.29 KB
nubus.h	8.17 KB
nvme_ioctl.h	1.55 KB
nvram.h	469 B
omap3isp.h	20.19 KB
omapfb.h	5.72 KB
oom.h	448 B
openvswitch.h	31.79 KB
packet_diag.h	1.5 KB
param.h	78 B
parport.h	3.56 KB
patchkey.h	829 B
pci.h	1.29 KB
pci_regs.h	49.96 KB
perf_event.h	29.53 KB
personality.h	1.99 KB
pfkeyv2.h	9.91 KB
pg.h	2.23 KB
phantom.h	1.55 KB
phonet.h	4.51 KB
pkt_cls.h	11.51 KB
pkt_sched.h	19.75 KB
pktcdvd.h	2.56 KB
pmu.h	5.13 KB
poll.h	22 B
posix_types.h	1.01 KB
ppdev.h	3.07 KB
ppp-comp.h	2.41 KB
ppp-ioctl.h	5.29 KB
ppp_defs.h	4.93 KB
pps.h	4.06 KB
prctl.h	6.71 KB
psample.h	735 B
ptp_clock.h	4.69 KB
ptrace.h	3.2 KB
qnx4_fs.h	2.21 KB
qnxtypes.h	561 B
quota.h	5.78 KB
radeonfb.h	297 B
raid	-
random.h	1.2 KB
raw.h	302 B
rds.h	7.9 KB
reboot.h	1.25 KB
reiserfs_fs.h	712 B
reiserfs_xattr.h	464 B
resource.h	2.09 KB
rfkill.h	3.5 KB
romfs_fs.h	1.15 KB
rose.h	2.12 KB
route.h	2.21 KB
rtc.h	3.85 KB
rtnetlink.h	16.63 KB
scc.h	4.43 KB
sched.h	2.23 KB
screen_info.h	2.36 KB
sctp.h	29.29 KB
sdla.h	2.71 KB
seccomp.h	1.79 KB
securebits.h	2.58 KB
selinux_netlink.h	1.11 KB
sem.h	2.52 KB
serial.h	3.04 KB
serial_core.h	5.11 KB
serial_reg.h	15.66 KB
serio.h	1.77 KB
shm.h	2.17 KB
signal.h	171 B
signalfd.h	1.07 KB
snmp.h	12.38 KB
sock_diag.h	431 B
socket.h	738 B
sockios.h	5.89 KB
som.h	5.35 KB
sonet.h	2.17 KB
sonypi.h	5.12 KB
sound.h	1.15 KB
soundcard.h	44.96 KB
spi	-
stat.h	1 KB
stddef.h	1 B
string.h	175 B
sunrpc	-
suspend_ioctls.h	1.34 KB
swab.h	6.36 KB
synclink.h	8.71 KB
sysctl.h	25.46 KB
sysinfo.h	986 B
target_core_user.h	3.65 KB
taskstats.h	6.83 KB
tc_act	-
tc_ematch	-
tcp.h	5.93 KB
tcp_metrics.h	1.45 KB
telephony.h	8.84 KB
termios.h	443 B
time.h	1.54 KB
times.h	215 B
timex.h	6.17 KB
tiocl.h	1.63 KB
tipc.h	5.44 KB
tipc_config.h	14.1 KB
toshiba.h	1.24 KB
tty.h	1.33 KB
tty_flags.h	3.66 KB
types.h	1.4 KB
udf_fs_i.h	634 B
udp.h	1.28 KB
uhid.h	2.15 KB
uinput.h	5 KB
uio.h	668 B
ultrasound.h	4.39 KB
un.h	239 B
unistd.h	157 B
unix_diag.h	1.1 KB
usb	-
usbdevice_fs.h	6.56 KB
userfaultfd.h	6.59 KB
utime.h	152 B
utsname.h	606 B
uuid.h	1.5 KB
uvcvideo.h	1.6 KB
v4l2-common.h	2.38 KB
v4l2-controls.h	37.34 KB
v4l2-dv-timings.h	25.75 KB
v4l2-mediabus.h	4.55 KB
v4l2-subdev.h	5.27 KB
version.h	255 B
veth.h	402 B
vfio.h	24.12 KB
vhost.h	7.13 KB
videodev2.h	67.41 KB
virtio_9p.h	1.99 KB
virtio_balloon.h	3.71 KB
virtio_blk.h	5.2 KB
virtio_config.h	3.24 KB
virtio_console.h	2.94 KB
virtio_gpu.h	7.84 KB
virtio_ids.h	2.32 KB
virtio_input.h	2.45 KB
virtio_net.h	9.4 KB
virtio_pci.h	6.63 KB
virtio_ring.h	6.18 KB
virtio_rng.h	265 B
virtio_scsi.h	5.13 KB
virtio_types.h	2.11 KB
virtio_vsock.h	3.01 KB
vm_sockets.h	5.13 KB
vsockmon.h	1.78 KB
vt.h	3.05 KB
vtpm_proxy.h	1.62 KB
vzcalluser.h	4.11 KB
vzctl_netstat.h	2.56 KB
vzctl_venet.h	641 B
vzctl_veth.h	758 B
vziptable_defs.h	3.03 KB
vzlist.h	845 B
wait.h	600 B
wanrouter.h	390 B
watchdog.h	2.22 KB
wimax	-
wimax.h	8.17 KB
wireless.h	41.65 KB
x25.h	3.42 KB
xattr.h	2.53 KB
xfrm.h	11 KB

Edit: serial_reg.h

/*
 * include/linux/serial_reg.h
 *
 * Copyright (C) 1992, 1994 by Theodore Ts'o.
 * 
 * Redistribution of this file is permitted under the terms of the GNU 
 * Public License (GPL)
 * 
 * These are the UART port assignments, expressed as offsets from the base
 * register.  These assignments should hold for any serial port based on
 * a 8250, 16450, or 16550(A).
 */

#ifndef _LINUX_SERIAL_REG_H
#define _LINUX_SERIAL_REG_H

/*
 * DLAB=0
 */
#define UART_RX		0	/* In:  Receive buffer */
#define UART_TX		0	/* Out: Transmit buffer */

#define UART_IER	1	/* Out: Interrupt Enable Register */
#define UART_IER_MSI		0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI		0x01 /* Enable receiver data interrupt */
/*
 * Sleep mode for ST16650 and TI16750.  For the ST16650, EFR[4]=1
 */
#define UART_IERX_SLEEP		0x10 /* Enable sleep mode */

#define UART_IIR	2	/* In:  Interrupt ID Register */
#define UART_IIR_NO_INT		0x01 /* No interrupts pending */
#define UART_IIR_ID		0x06 /* Mask for the interrupt ID */
#define UART_IIR_MSI		0x00 /* Modem status interrupt */
#define UART_IIR_THRI		0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI		0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI		0x06 /* Receiver line status interrupt */

#define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */

#define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
#define UART_IIR_XOFF		0x10 /* OMAP XOFF/Special Character */
#define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */

#define UART_FCR	2	/* Out: FIFO Control Register */
#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
/*
 * Note: The FIFO trigger levels are chip specific:
 *	RX:76 = 00  01  10  11	TX:54 = 00  01  10  11
 * PC16550D:	 1   4   8  14		xx  xx  xx  xx
 * TI16C550A:	 1   4   8  14          xx  xx  xx  xx
 * TI16C550C:	 1   4   8  14          xx  xx  xx  xx
 * ST16C550:	 1   4   8  14		xx  xx  xx  xx
 * ST16C650:	 8  16  24  28		16   8  24  30	PORT_16650V2
 * NS16C552:	 1   4   8  14		xx  xx  xx  xx
 * ST16C654:	 8  16  56  60		 8  16  32  56	PORT_16654
 * TI16C750:	 1  16  32  56		xx  xx  xx  xx	PORT_16750
 * TI16C752:	 8  16  56  60		 8  16  32  56
 * Tegra:	 1   4   8  14		16   8   4   1	PORT_TEGRA
 */
#define UART_FCR_R_TRIG_00	0x00
#define UART_FCR_R_TRIG_01	0x40
#define UART_FCR_R_TRIG_10	0x80
#define UART_FCR_R_TRIG_11	0xc0
#define UART_FCR_T_TRIG_00	0x00
#define UART_FCR_T_TRIG_01	0x10
#define UART_FCR_T_TRIG_10	0x20
#define UART_FCR_T_TRIG_11	0x30

#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
/* 16650 definitions */
#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
#define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode (TI16C750) */

#define UART_LCR	3	/* Out: Line Control Register */
/*
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 */
#define UART_LCR_DLAB		0x80 /* Divisor latch access bit */
#define UART_LCR_SBC		0x40 /* Set break control */
#define UART_LCR_SPAR		0x20 /* Stick parity (?) */
#define UART_LCR_EPAR		0x10 /* Even parity select */
#define UART_LCR_PARITY		0x08 /* Parity Enable */
#define UART_LCR_STOP		0x04 /* Stop bits: 0=1 bit, 1=2 bits */
#define UART_LCR_WLEN5		0x00 /* Wordlength: 5 bits */
#define UART_LCR_WLEN6		0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7		0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8		0x03 /* Wordlength: 8 bits */

/*
 * Access to some registers depends on register access / configuration
 * mode.
 */
#define UART_LCR_CONF_MODE_A	UART_LCR_DLAB	/* Configutation mode A */
#define UART_LCR_CONF_MODE_B	0xBF		/* Configutation mode B */

#define UART_MCR	4	/* Out: Modem Control Register */
#define UART_MCR_CLKSEL		0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
#define UART_MCR_TCRTLR		0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
#define UART_MCR_XONANY		0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
#define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
#define UART_MCR_LOOP		0x10 /* Enable loopback test mode */
#define UART_MCR_OUT2		0x08 /* Out2 complement */
#define UART_MCR_OUT1		0x04 /* Out1 complement */
#define UART_MCR_RTS		0x02 /* RTS complement */
#define UART_MCR_DTR		0x01 /* DTR complement */

#define UART_LSR	5	/* In:  Line Status Register */
#define UART_LSR_FIFOE		0x80 /* Fifo error */
#define UART_LSR_TEMT		0x40 /* Transmitter empty */
#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI		0x10 /* Break interrupt indicator */
#define UART_LSR_FE		0x08 /* Frame error indicator */
#define UART_LSR_PE		0x04 /* Parity error indicator */
#define UART_LSR_OE		0x02 /* Overrun error indicator */
#define UART_LSR_DR		0x01 /* Receiver data ready */
#define UART_LSR_BRK_ERROR_BITS	0x1E /* BI, FE, PE, OE bits */

#define UART_MSR	6	/* In:  Modem Status Register */
#define UART_MSR_DCD		0x80 /* Data Carrier Detect */
#define UART_MSR_RI		0x40 /* Ring Indicator */
#define UART_MSR_DSR		0x20 /* Data Set Ready */
#define UART_MSR_CTS		0x10 /* Clear to Send */
#define UART_MSR_DDCD		0x08 /* Delta DCD */
#define UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR		0x02 /* Delta DSR */
#define UART_MSR_DCTS		0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA	0x0F /* Any of the delta bits! */

#define UART_SCR	7	/* I/O: Scratch Register */

/*
 * DLAB=1
 */
#define UART_DLL	0	/* Out: Divisor Latch Low */
#define UART_DLM	1	/* Out: Divisor Latch High */

/*
 * LCR=0xBF (or DLAB=1 for 16C660)
 */
#define UART_EFR	2	/* I/O: Extended Features Register */
#define UART_XR_EFR	9	/* I/O: Extended Features Register (XR17D15x) */
#define UART_EFR_CTS		0x80 /* CTS flow control */
#define UART_EFR_RTS		0x40 /* RTS flow control */
#define UART_EFR_SCD		0x20 /* Special character detect */
#define UART_EFR_ECB		0x10 /* Enhanced control bit */
/*
 * the low four bits control software flow control
 */

/*
 * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
 */
#define UART_XON1	4	/* I/O: Xon character 1 */
#define UART_XON2	5	/* I/O: Xon character 2 */
#define UART_XOFF1	6	/* I/O: Xoff character 1 */
#define UART_XOFF2	7	/* I/O: Xoff character 2 */

/*
 * EFR[4]=1 MCR[6]=1, TI16C752
 */
#define UART_TI752_TCR	6	/* I/O: transmission control register */
#define UART_TI752_TLR	7	/* I/O: trigger level register */

/*
 * LCR=0xBF, XR16C85x
 */
#define UART_TRG	0	/* FCTR bit 7 selects Rx or Tx
				 * In: Fifo count
				 * Out: Fifo custom trigger levels */
/*
 * These are the definitions for the Programmable Trigger Register
 */
#define UART_TRG_1		0x01
#define UART_TRG_4		0x04
#define UART_TRG_8		0x08
#define UART_TRG_16		0x10
#define UART_TRG_32		0x20
#define UART_TRG_64		0x40
#define UART_TRG_96		0x60
#define UART_TRG_120		0x78
#define UART_TRG_128		0x80

#define UART_FCTR	1	/* Feature Control Register */
#define UART_FCTR_RTS_NODELAY	0x00  /* RTS flow control delay */
#define UART_FCTR_RTS_4DELAY	0x01
#define UART_FCTR_RTS_6DELAY	0x02
#define UART_FCTR_RTS_8DELAY	0x03
#define UART_FCTR_IRDA		0x04  /* IrDa data encode select */
#define UART_FCTR_TX_INT	0x08  /* Tx interrupt type select */
#define UART_FCTR_TRGA		0x00  /* Tx/Rx 550 trigger table select */
#define UART_FCTR_TRGB		0x10  /* Tx/Rx 650 trigger table select */
#define UART_FCTR_TRGC		0x20  /* Tx/Rx 654 trigger table select */
#define UART_FCTR_TRGD		0x30  /* Tx/Rx 850 programmable trigger select */
#define UART_FCTR_SCR_SWAP	0x40  /* Scratch pad register swap */
#define UART_FCTR_RX		0x00  /* Programmable trigger mode select */
#define UART_FCTR_TX		0x80  /* Programmable trigger mode select */

/*
 * LCR=0xBF, FCTR[6]=1
 */
#define UART_EMSR	7	/* Extended Mode Select Register */
#define UART_EMSR_FIFO_COUNT	0x01  /* Rx/Tx select */
#define UART_EMSR_ALT_COUNT	0x02  /* Alternating count select */

/*
 * The Intel XScale on-chip UARTs define these bits
 */
#define UART_IER_DMAE	0x80	/* DMA Requests Enable */
#define UART_IER_UUE	0x40	/* UART Unit Enable */
#define UART_IER_NRZE	0x20	/* NRZ coding Enable */
#define UART_IER_RTOIE	0x10	/* Receiver Time Out Interrupt Enable */

#define UART_IIR_TOD	0x08	/* Character Timeout Indication Detected */

#define UART_FCR_PXAR1	0x00	/* receive FIFO threshold = 1 */
#define UART_FCR_PXAR8	0x40	/* receive FIFO threshold = 8 */
#define UART_FCR_PXAR16	0x80	/* receive FIFO threshold = 16 */
#define UART_FCR_PXAR32	0xc0	/* receive FIFO threshold = 32 */

/*
 * Intel MID on-chip HSU (High Speed UART) defined bits
 */
#define UART_FCR_HSU_64_1B	0x00	/* receive FIFO treshold = 1 */
#define UART_FCR_HSU_64_16B	0x40	/* receive FIFO treshold = 16 */
#define UART_FCR_HSU_64_32B	0x80	/* receive FIFO treshold = 32 */
#define UART_FCR_HSU_64_56B	0xc0	/* receive FIFO treshold = 56 */

#define UART_FCR_HSU_16_1B	0x00	/* receive FIFO treshold = 1 */
#define UART_FCR_HSU_16_4B	0x40	/* receive FIFO treshold = 4 */
#define UART_FCR_HSU_16_8B	0x80	/* receive FIFO treshold = 8 */
#define UART_FCR_HSU_16_14B	0xc0	/* receive FIFO treshold = 14 */

#define UART_FCR_HSU_64B_FIFO	0x20	/* chose 64 bytes FIFO */
#define UART_FCR_HSU_16B_FIFO	0x00	/* chose 16 bytes FIFO */

#define UART_FCR_HALF_EMPT_TXI	0x00	/* trigger TX_EMPT IRQ for half empty */
#define UART_FCR_FULL_EMPT_TXI	0x08	/* trigger TX_EMPT IRQ for full empty */

/*
 * These register definitions are for the 16C950
 */
#define UART_ASR	0x01	/* Additional Status Register */
#define UART_RFL	0x03	/* Receiver FIFO level */
#define UART_TFL 	0x04	/* Transmitter FIFO level */
#define UART_ICR	0x05	/* Index Control Register */

/* The 16950 ICR registers */
#define UART_ACR	0x00	/* Additional Control Register */
#define UART_CPR	0x01	/* Clock Prescalar Register */
#define UART_TCR	0x02	/* Times Clock Register */
#define UART_CKS	0x03	/* Clock Select Register */
#define UART_TTL	0x04	/* Transmitter Interrupt Trigger Level */
#define UART_RTL	0x05	/* Receiver Interrupt Trigger Level */
#define UART_FCL	0x06	/* Flow Control Level Lower */
#define UART_FCH	0x07	/* Flow Control Level Higher */
#define UART_ID1	0x08	/* ID #1 */
#define UART_ID2	0x09	/* ID #2 */
#define UART_ID3	0x0A	/* ID #3 */
#define UART_REV	0x0B	/* Revision */
#define UART_CSR	0x0C	/* Channel Software Reset */
#define UART_NMR	0x0D	/* Nine-bit Mode Register */
#define UART_CTR	0xFF

/*
 * The 16C950 Additional Control Register
 */
#define UART_ACR_RXDIS	0x01	/* Receiver disable */
#define UART_ACR_TXDIS	0x02	/* Transmitter disable */
#define UART_ACR_DSRFC	0x04	/* DSR Flow Control */
#define UART_ACR_TLENB	0x20	/* 950 trigger levels enable */
#define UART_ACR_ICRRD	0x40	/* ICR Read enable */
#define UART_ACR_ASREN	0x80	/* Additional status enable */

/*
 * These definitions are for the RSA-DV II/S card, from
 *
 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
 */

#define UART_RSA_BASE (-8)

#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */

#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */

#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */

#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */

#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */

#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */

#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */

#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */

#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */

#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */

/*
 * The RSA DSV/II board has two fixed clock frequencies.  One is the
 * standard rate, and the other is 8 times faster.
 */
#define SERIAL_RSA_BAUD_BASE (921600)
#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)

/*
 * Extra serial register definitions for the internal UARTs
 * in TI OMAP processors.
 */
#define UART_OMAP_MDR1		0x08	/* Mode definition register */
#define UART_OMAP_MDR2		0x09	/* Mode definition register 2 */
#define UART_OMAP_SCR		0x10	/* Supplementary control register */
#define UART_OMAP_SSR		0x11	/* Supplementary status register */
#define UART_OMAP_EBLR		0x12	/* BOF length register */
#define UART_OMAP_OSC_12M_SEL	0x13	/* OMAP1510 12MHz osc select */
#define UART_OMAP_MVER		0x14	/* Module version register */
#define UART_OMAP_SYSC		0x15	/* System configuration register */
#define UART_OMAP_SYSS		0x16	/* System status register */
#define UART_OMAP_WER		0x17	/* Wake-up enable register */

/*
 * These are the definitions for the MDR1 register
 */
#define UART_OMAP_MDR1_16X_MODE		0x00	/* UART 16x mode */
#define UART_OMAP_MDR1_SIR_MODE		0x01	/* SIR mode */
#define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
#define UART_OMAP_MDR1_13X_MODE		0x03	/* UART 13x mode */
#define UART_OMAP_MDR1_MIR_MODE		0x04	/* MIR mode */
#define UART_OMAP_MDR1_FIR_MODE		0x05	/* FIR mode */
#define UART_OMAP_MDR1_CIR_MODE		0x06	/* CIR mode */
#define UART_OMAP_MDR1_DISABLE		0x07	/* Disable (default state) */

/*
 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
 */
#define UART_EXAR_8XMODE	0x88	/* 8X sampling rate select */
#define UART_EXAR_SLEEP		0x8b	/* Sleep mode */
#define UART_EXAR_DVID		0x8d	/* Device identification */

#define UART_EXAR_FCTR		0x08	/* Feature Control Register */
#define UART_FCTR_EXAR_IRDA	0x08	/* IrDa data encode select */
#define UART_FCTR_EXAR_485	0x10	/* Auto 485 half duplex dir ctl */
#define UART_FCTR_EXAR_TRGA	0x00	/* FIFO trigger table A */
#define UART_FCTR_EXAR_TRGB	0x60	/* FIFO trigger table B */
#define UART_FCTR_EXAR_TRGC	0x80	/* FIFO trigger table C */
#define UART_FCTR_EXAR_TRGD	0xc0	/* FIFO trigger table D programmable */

#define UART_EXAR_TXTRG		0x0a	/* Tx FIFO trigger level write-only */
#define UART_EXAR_RXTRG		0x0b	/* Rx FIFO trigger level write-only */

#endif /* _LINUX_SERIAL_REG_H */